1. Field of the Invention
The present invention relates to a semiconductor device having a termination structure which is an electric field relaxing structure provided in a device termination region and a manufacturing method thereof, and more particularly, to a semiconductor device capable of reducing an area occupied by a termination structure while maintaining a stable withstand voltage and a manufacturing method thereof.
2. Background Art
Power devices are semiconductor elements mainly intended for power apparatuses used for power conversion, power control or the like and designed to have a higher withstand voltage and a higher current than those of normal semiconductor elements. The power devices need to shut off a current when a reverse voltage is applied and maintain a high voltage. As methods of increasing a withstand voltage of a power device, a termination structure such as an FLR (field limiting ring) structure and a field plate structure are disclosed (e.g., see The Institute of Electrical Engineers of Japan, edited by Electron Device Society Power Device & IC Technical Committee, “Power Device/Power IC Handbook,” CORONA PUBLISHING CO., LTD., p54 to 64 and 170 to 174).
Of these structures, the FLR structure is a structure in which a principal junction made up of a low concentration n-type impurity region and a p-type impurity region formed on an inner surface of the n-type impurity region is surrounded by a plurality of ring-shaped p-type impurity regions. This structure relaxes an electric field of a substrate surface and maintains a withstand voltage.
However, since the FLR structure relaxes the electric field in the low concentration n-type impurity region located between the plurality of ring-shaped p-type impurity regions, when the withstand voltage of the semiconductor device is increased using the FLR structure, there is a problem that the area of the outer circumferential portion of the principal junction increases, resulting in an increase in the area occupied by the semiconductor device.
In contrast, a semiconductor device is proposed which is provided with a termination structure that maintains a withstand voltage using a p-type RESURF layer which is an impurity layer set to an impurity concentration and a depth that satisfy RESURF conditions under which when a high reverse voltage to be maintained is applied, the p-type RESURF layer is completely depleted (e.g., see Japanese Patent Laid-Open No. 2010-245281). This eliminates the necessity for forming a plurality of ring-shaped p-type impurity regions to maintain the withstand voltage, and can thereby reduce the area occupied by the termination structure while maintaining the withstand voltage.